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Description: ALLEGRO 约束规则设置步骤（以DDR 为例）,同样为pdf格式方便大家下载使用
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Size: 218416 |
Author: zhang |
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Description: ddr sram的官方文档,介绍了ddr sram的使用及其接口等各方面的消息资料.-ddr sram official documents, ddr sram introduced the use of its interface and other sources of information.
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Size: 452608 |
Author: wang |
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Description: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
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Size: 124928 |
Author: |
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Description: 关于DDR，DDR2,DDR3和MMC的标准规范。-On the DDR, DDR2, DDR3 and the MMC standards.
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Size: 13941760 |
Author: 崔海群 |
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Description: ALLEGRO 约束规则设置步骤（以DDR 为例）,同样为pdf格式方便大家下载使用-ALLEGRO bound by the rules set up steps (to DDR as an example), the same for everyone to download pdf format to facilitate the use of
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Size: 218112 |
Author: zhang |
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Description: 128Mb DDR verilog源程序-128Mb DDR verilog source code
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Size: 23552 |
Author: tiantian |
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Description: S3C6410 線路設計時一定要參考的文件,尤其是DDR Layout guide一定要看.以免開發出的板子不能動.-S3C6410 circuit design must read this documents, especially DDR Layout guide. To avoid your board can not run in high speed.
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Size: 2451456 |
Author: 呂宜有 |
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Description: SATA NAS SOC，200MHz ARM926EJS核 SATA接口的NAS用处理器，集成USB2.0 HOST接口，Ethernet控制器，DDR SDRAM控制器，PCI HOST接口，可以扩展PCI外设。-SATA NAS SOC，NAS COntroller with 200MHz ARM926EJS core, intergated SATA controller，USB2.0 HOST controller，Ethernet MAC controller，DDR SDRAM controller，PCI HOST。
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Size: 974848 |
Author: gxliu |
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Description: 关于ddr sdram的一篇不错的文章，讲得挺详细的。-a good paper about ddr sdram，teaching you how to use ddr sdram.
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Size: 57344 |
Author: 张涛 |
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Description: DDR SDRAM设计及调试经验总结.pdf
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Size: 338944 |
Author: arens09 |
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Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。
debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考
RTL Coding and Optimization Guide for use with Design Compiler.pdf
数提讲座（1）.wmv
数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。
ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。
基于DDR SDRAM控制时序分析的模型.pdf
全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。
数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真.
-i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference.
debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference
RTL Coding and Optimization Guide for use with Design Compiler.pdf
Mention the number of lectures (1). Wmv
Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look.
ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese .
DDR SDRAM control the timing analysis based on the model. Pdf
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Size: 20989952 |
Author: 喻琪 |
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Description: K3(Hi3611) 多媒体处理器研发指导手册(华为内部47页研发文档)-K3 (Hi3611) multimedia processor developed guidelines (Huawei R & D within the 47 documents)
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Size: 369664 |
Author: MichaelC |
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Description: DDR SDRAM设计及调试经验总结.pdf-DDR SDRAM design and debug Experience. Pdf
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Size: 338944 |
Author: Mike |
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Description: The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features:
• Spartan-3E FPGA specific features • Parallel NOR Flash configuration • MultiBoot FPGA configuration from Parallel NOR Flash PROM • SPI serial Flash configuration
• Embedded development • MicroBlazeTM 32-bit embedded RISC processor • PicoBlazeTM 8-bit embedded controller • DDR memory interfaces
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Size: 5851136 |
Author: Akalu Lentiro |
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Description: JEDEC DDR 2 memory interface specification document
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Size: 988160 |
Author: mahatma |
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Description: ddr接口电气标准，jdec sstl_3，pdf文档-jdec sstl 3.3v spec
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Size: 277504 |
Author: 范俊 |
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Description: M1671 - P4 Super North Bridge –
CPU, AGP, PCI and
Memory Controller
The M1671 is a high-performance, high-value North Bridge that supports all Pentium 4 processors. With internal 128-bit
architecture optimized for CPU bus, DDR and AGP4X interface, the M1671 has outstanding high system performance under all
types of system operations. The M1671 also has a complete set of mobile features which makes the M1671 an ideal solution
for mobile systems.
Pdf Datasheet-M1671 - P4 Super North Bridge –
CPU, AGP, PCI and
Memory Controller
The M1671 is a high-performance, high-value North Bridge that supports all Pentium 4 processors. With internal 128-bit
architecture optimized for CPU bus, DDR and AGP4X interface, the M1671 has outstanding high system performance under all
types of system operations. The M1671 also has a complete set of mobile features which makes the M1671 an ideal solution
for mobile systems.
Pdf Datasheet
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Size: 1119232 |
Author: serge |
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Description: 全志v3s的datasheet。详细的寄存器说明。
全志v3s介绍：内置64M ddr内存，qfp封装(V3s of datasheet. Detailed register instructions.
Whole chronicles v3s introduction: built in 64M DDR memory, QFP package)
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Size: 5023744 |
Author: ______
|
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Description: JEDC DDR-5 Standard. DDR-5 标准。(JEDC DDR-5 Standard. JESD79-5 DDR5 Spec Early Draft Rev0.1)
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Size: 4538368 |
Author: Vkings |
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